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53 lines
2.8 KiB
Plaintext
53 lines
2.8 KiB
Plaintext
// Module included in the following assemblies:
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//
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// * networking/ptp/about-ptp.adoc
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:_mod-docs-content-type: CONCEPT
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[id="ptp-dual-nics_{context}"]
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= 2-card E810 NIC configuration reference
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{product-title} supports single and dual-NIC Intel E810 hardware for PTP timing in grandmaster clocks (T-GM) and boundary clocks (T-BC).
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Dual NIC grandmaster clock::
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--
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You can use a cluster host that has dual-NIC hardware as PTP grandmaster clock.
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One NIC receives timing information from the global navigation satellite system (GNSS).
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The second NIC receives the timing information from the first using the SMA1 Tx/Rx connections on the E810 NIC faceplate.
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The system clock on the cluster host is synchronized from the NIC that is connected to the GNSS satellite.
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Dual NIC grandmaster clocks are a feature of distributed RAN (D-RAN) configurations where the Remote Radio Unit (RRU) and Baseband Unit (BBU) are located at the same radio cell site.
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D-RAN distributes radio functions across multiple sites, with backhaul connections linking them to the core network.
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.Dual NIC grandmaster clock
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image::openshift-ptp-using-dual-nic-ptp.png[Dual NIC PTP grandmaster clock connected to GNSS timing source and downstream PTP boundary and ordinary clocks]
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[NOTE]
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====
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In a dual-NIC T-GM configuration, a single `ts2phc` program operate on two PTP hardware clocks (PHCs), one for each NIC.
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====
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--
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Dual NIC boundary clock::
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--
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For 5G telco networks that deliver mid-band spectrum coverage, each virtual distributed unit (vDU) requires connections to 6 radio units (RUs). To make these connections, each vDU host requires 2 NICs configured as boundary clocks.
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Dual NIC hardware allows you to connect each NIC to the same upstream leader clock with separate `ptp4l` instances for each NIC feeding the downstream clocks.
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--
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Highly available system clock with dual-NIC boundary clocks::
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--
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You can configure Intel E810-XXVDA4 Salem channel dual-NIC hardware as dual PTP boundary clocks that provide timing for a highly available system clock.
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This configuration is useful when you have multiple time sources on different NICs.
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High availability ensures that the node does not lose timing synchronization if one of the two timing sources is lost or disconnected.
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Each NIC is connected to the same upstream leader clock.
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Highly available boundary clocks use multiple PTP domains to synchronize with the target system clock.
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When a T-BC is highly available, the host system clock can maintain the correct offset even if one or more `ptp4l` instances syncing the NIC PHC clock fails.
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If any single SFP port or cable failure occurs, the boundary clock stays in sync with the leader clock.
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Boundary clock leader source selection is done using the A-BMCA algorithm. For more information, see link:https://www.itu.int/rec/T-REC-G.8275.1/en[ITU-T recommendation G.8275.1].
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--
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