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60 lines
2.6 KiB
Plaintext
60 lines
2.6 KiB
Plaintext
// Module included in the following assemblies:
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//
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// * networking/ptp/configuring-ptp.adoc
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:_mod-docs-content-type: REFERENCE
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[id="nw-ptp-dual-e810-hardware-config-reference_{context}"]
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= Dual E810 NIC configuration reference
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Use this information to understand how to use the link:https://github.com/openshift/linuxptp-daemon/blob/release-4.14/addons/intel/e810.go[Intel E810 hardware plugin] to configure a pair of E810 network interfaces as PTP grandmaster clock (T-GM).
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Before you configure the dual-NIC cluster host, you must connect the two NICs with an SMA1 cable using the 1PPS faceplace connections.
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When you configure a dual-NIC T-GM, you need to compensate for the 1PPS signal delay that occurs when you connect the NICs using the SMA1 connection ports.
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Various factors such as cable length, ambient temperature, and component and manufacturing tolerances can affect the signal delay.
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To compensate for the delay, you must calculate the specific value that you use to offset the signal delay.
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.E810 dual-NIC T-GM PtpConfig CR reference
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[cols="1,2" width="90%", options="header"]
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|====
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|PtpConfig field
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|Description
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|`spec.profile.plugins.e810.pins`
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a|Configure the E810 hardware pins using the PTP Operator E810 hardware plugin.
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* Pin `2 1` enables the `1PPS OUT` connection for `SMA1` on NIC one.
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* Pin `1 1` enables the `1PPS IN` connection for `SMA1` on NIC two.
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|`spec.profile.ts2phcConf`
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|Use the `ts2phcConf` field to configure parameters for NIC one and NIC two.
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Set `ts2phc.master 0` for NIC two.
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This configures the timing source for NIC two from the 1PPS input, not GNSS.
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Configure the `ts2phc.extts_correction` value for NIC two to compensate for the delay that is incurred for the specific SMA cable and cable length that you use.
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The value that you configure depends on your specific measurements and SMA1 cable length.
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|`spec.profile.ptp4lConf`
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|Set the value of `boundary_clock_jbod` to 1 to enable support for multiple NICs.
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|====
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Each value in the `spec.profile.plugins.e810.pins` list follows the `<function>` `<channel_number>` format.
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Where:
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`<function>`: Specifies the pin role. The following values are associated with the pin role:
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* `0`: Disabled
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* `1`: Receive (Rx) – for 1PPS IN
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* `2`: Transmit (Tx) – for 1PPS OUT
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`<channel_number>`: A number associated with the physical connector. The following channel numbers are associated with the physical connectors:
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* `1`: `SMA1` or `U.FL1`
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* `2`: `SMA2` or `U.FL2`
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Examples:
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* `2 1`: Enables `1PPS OUT` (Tx) on `SMA1`.
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* `1 1`: Enables `1PPS IN` (Rx) on `SMA1`.
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The PTP Operator passes these values to the Intel E810 hardware plugin and writes them to the sysfs pin configuration interface on each NIC. |